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5 Z0 \, I" p, h DATE: 05-01-2015 HOTFIX VERSION: 002: `9 l7 a, |# I5 K8 [
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' J K/ @1 }# l0 o( Y CCRID PRODUCT PRODUCTLEVEL2 TITLE
$ D. H' C7 o& {. O3 Z ===================================================================================================================================
0 j& @; |2 b( B& r; Z L0 t% e 1315048 allegro_EDITOR INTERFACES IPC2581 translation inconsistency on negative layer
; y. H0 z! h" d r* _ 1362745 CONSTRAINT_MGR OTHER Allegro PCB Editor crashes on opening Constraint Manager with any design
& Z' J6 O( N5 e2 h' D) S0 P/ t8 u 1373412 ALLEGRO_EDITOR GRAPHICS SigXP Print Canvas : Via model seems to be filled by black Via box.0 {6 G6 V) x5 b( K
1376765 CONSTRAINT_MGR ANALYSIS SETUP/Hold spreadsheet lists only one pin pair
2 o5 d7 b# `( j9 E. h1 H$ m 1399646 ASI_SI OTHER Should be able to run mbs2brd with SI/PI base licenses" o! x) u& R1 J$ X" v0 Q
1400215 SIG_INTEGRITY REPORTS cross talk failure on certain nets in PCB SI 16.6
& C' e7 V" S% Z4 I. u 1400302 ALLEGRO_EDITOR MANUFACT Copper Thieving is working differently in SPB16.6 as compared to SPB16.5+ B: m; n* L( C3 b
1400755 ALLEGRO_EDITOR SHAPE Updating the shapes on the ATTACHED deisgn causes a short to a pad.
8 J& J' h. Z+ {! A; i" | 1400813 ALLEGRO_EDITOR SHAPE PCB Editor crashes when you delete islands from all the layers and save the board
8 w$ p! X/ a% F" \; c; U4 Q 1404174 SIP_LAYOUT OTHER Creating bounding shapes generates INCORRECT shapes and DRCs) C7 m3 g" L' T' x& K% @. d7 `. V; B' Y
1404184 ALLEGRO_EDITOR INTERFACES Step package mapping - Save is disabled for certain symbol9 `7 C$ r, |4 r6 c- _
1406457 ALLEGRO_EDITOR SCRIPTS Unable to launch allegro.exe -orcad after update hotfix 0460 z9 V. M) E' N
1407123 ALLEGRO_EDITOR OTHER Lines with zero line width are not being printed in PDF format
; A" e- n: L! n 1407483 ALLEGRO_EDITOR REFRESH The 'refresh symbol' command creates an unrouted connection in a fully routed design
, t& d3 p8 N+ a4 d 1408072 SIP_LAYOUT OTHER Net assignment for a BGA component fails on running the File - Import - Netlist-in wizard command.8 k) _ b; {2 v
1410857 ALLEGRO_EDITOR DRC_CONSTR Diff Pair Uncoupled length DRC gives different results in SPB16.3, SPB16.5, and SPB16.6.* w, d/ A! s3 p& a/ r& _
1413235 ALLEGRO_EDITOR INTERACTIV Find by Query with Via Structures: GUI freeze M; C) e/ }8 d% k4 \( X* ^6 ]
0 J s! a' l! O DATE: 04-03-2015 HOTFIX VERSION: 0013 j/ B! l( O; i
===================================================================================================================================
" [0 H( i$ g9 ] CCRID PRODUCT PRODUCTLEVEL2 TITLE
& R# A$ ~' O; D- H4 l' g =================================================================================================================================== q4 V+ z3 x/ R& o! s0 J
491042 concept_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
5 m; W S# ?; T! h; @. @$ P1 @# l9 ~ 1205900 ALLEGRO_EDITOR INTERACTIV additional object polygon-rectangle for "snap to pick", ?* `, |- Z8 _- @6 {# w* w
1327533 SIP_LAYOUT REPORTS Metal Usage Report fails% C. k5 T9 l! M, w
1341177 ALLEGRO_EDITOR PLACEMENT "Place Replicate Unmatched Component Interface" window size should be increased to show "Matched Component"
6 `, x- K2 e6 j; u 1360269 SIP_LAYOUT REPORTS Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set2 m. H0 d9 j" _8 }! Y" y
1361281 ALLEGRO_EDITOR INTERACTIV Moving stacked vs non-stacked via's should be the same./ `* W" \# q/ j e5 x. u
1366525 ALLEGRO_EDITOR INTERACTIV Add replace via with via structure command to Allegro PCB
. n% ^1 ]3 g7 u8 f% f 1368091 ALLEGRO_EDITOR INTERACTIV Snap pick to fuction should see fiiled rectangle as a shape
) n, S1 V9 L& j3 u7 Y0 [, R' P0 s 1371510 APD DATABASE How to show DRC when tack point of wirebond out of finger boundary
+ O& d/ G- D& C1 X2 X* a- Y- p% K" N" Y 1373564 ASI_PI GUI Impedance results are incorrect in PFE
9 w1 X* l7 P+ J* s6 c 1374703 ALLEGRO_EDITOR SHAPE Inconsistent behavior on shape voiding
' F$ g8 k% V7 Z" T 1376851 CONSTRAINT_MGR UI_FORMS CM workbooks change after simulating, Z9 X6 u! M) X" V1 V! q$ Z
1377555 ALLEGRO_EDITOR DRC_CONSTR The "Line to SMD Pin Same Net Spacing" DRC toggles everytime we run "Force Update" of Dynamic Shapes.9 M2 k' c2 ? m" W$ D
1378032 ALLEGRO_EDITOR REPORTS Report command and batch mode give different Waived DRC Report results in PCB Editor v' I* f! D* e$ U& U& Z
1378611 ALLEGRO_EDITOR INTERFACES Enable STEP export to convert the mixed unit into one single unit; ]+ Q6 [% H% {2 @3 E0 O7 P
1379240 APD PLACEMENT Placement gives error regarding the difference in units between the database and symbol, which is not the case
) v/ a" c$ ?$ {3 p @ 1394908 ALLEGRO_EDITOR DATABASE Database crashes on doing "Show Element" on selected net9 V: @9 \$ |/ f- C
1395541 ALLEGRO_EDITOR PLOTTING Export PDF not correct for Phantom lines/ V5 j( k1 |: R# b7 p: c [- e
1395747 CONSTRAINT_MGR INTERACTIV Rename refdes causes Allegro to crash. Possibly due to CM being open.
' r: [8 o+ X* }; T3 h 1396915 APD STREAM_IF The question about MIRROR geometry function from stream out
% w3 q- P" Y: ~+ P8 f. c 1398184 ALLEGRO_EDITOR MANUFACT Mismatch in backdrill data with IPC-2581 export |
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发表于 2015-5-7 02:28
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发表于 2015-5-8 11:30
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