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Cadence迎来了Hotfix_SPB17.00.002_wint_1of1补丁

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1#
发表于 2015-5-7 02:28 | 只看该作者 回帖奖励 |倒序浏览 |阅读模式

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- i! @! D5 f$ O1 ^ DATE: 05-01-2015   HOTFIX VERSION: 002
: H- j8 p" G2 C* ?3 [' K( [: H ===================================================================================================================================
, k5 f) K: s# p7 [; q, ~6 T CCRID   PRODUCT        PRODUCTLEVEL2   TITLE) o/ H. X' q$ I' r
===================================================================================================================================
# ?# c6 a5 o/ Y7 A 1315048 allegro_EDITOR INTERFACES       IPC2581 translation inconsistency on negative layer
6 N+ c* K4 o5 ^* y: h  J2 c 1362745 CONSTRAINT_MGR OTHER            Allegro PCB Editor crashes on opening Constraint Manager with any design. R# n: o' H& _
1373412 ALLEGRO_EDITOR GRAPHICS         SigXP Print Canvas : Via model seems to be filled by black Via box.1 {5 E% A$ e9 A& l, B& i3 r" n
1376765 CONSTRAINT_MGR ANALYSIS        SETUP/Hold spreadsheet lists only one pin pair
$ }$ g6 v& ?, w3 H" k4 \* H; }: X- ? 1399646 ASI_SI         OTHER            Should be able to run mbs2brd with SI/PI base licenses9 O) _5 _8 v5 Q
1400215 SIG_INTEGRITY  REPORTS          cross talk failure on certain nets in PCB SI 16.6* |" j4 R* b/ z0 r5 z
1400302 ALLEGRO_EDITOR MANUFACT         Copper Thieving is working differently in SPB16.6 as compared to SPB16.5
9 ~2 Q; Z, Y0 v5 S 1400755 ALLEGRO_EDITOR SHAPE            Updating the shapes on the ATTACHED deisgn causes a short to a pad.
5 Y& D/ F- |  Z9 d% q  v  W5 ^ 1400813 ALLEGRO_EDITOR SHAPE            PCB Editor crashes when you delete islands from all the layers and save the board5 S6 m' X! z" c( [) o9 ^" G
1404174 SIP_LAYOUT     OTHER            Creating bounding shapes generates INCORRECT shapes and DRCs
# T/ k* M) E# V' `- k 1404184 ALLEGRO_EDITOR INTERFACES       Step package mapping - Save is disabled for certain symbol
9 J+ }; B8 z, Z8 N' T 1406457 ALLEGRO_EDITOR SCRIPTS          Unable to launch allegro.exe -orcad after update hotfix 046, A. J1 v" U6 D) G  o! d% M
1407123 ALLEGRO_EDITOR OTHER            Lines with zero line width are not being printed in PDF format. O3 g2 }2 N3 Z9 Q4 k7 J
1407483 ALLEGRO_EDITOR REFRESH          The 'refresh symbol' command creates an unrouted connection in a fully routed design
+ D8 @1 z) B! d9 X& B 1408072 SIP_LAYOUT     OTHER            Net assignment for a BGA component fails on running the File - Import - Netlist-in wizard command.) d# V# ~' U  ^) S6 `
1410857 ALLEGRO_EDITOR DRC_CONSTR       Diff Pair Uncoupled length DRC gives different results in SPB16.3,  SPB16.5, and SPB16.6./ Q1 i, J/ E! f0 a  d# R
1413235 ALLEGRO_EDITOR INTERACTIV       Find by Query with Via Structures: GUI freeze
/ i7 e! Z) R3 s
8 _! i" \: V2 ~: O* M& Q' P DATE: 04-03-2015   HOTFIX VERSION: 0011 r' t& L' m" T
===================================================================================================================================
7 C" u% @2 t/ I5 N7 j8 Z% S CCRID   PRODUCT        PRODUCTLEVEL2   TITLE1 e' _+ h7 Y/ |2 o; X
===================================================================================================================================$ o4 y6 u! G9 S) d% p& m% N! R& i
491042  concept_HDL    SECTION          Prevent PackagerXL from changing visibility on SEC attribute0 k4 p9 C. C1 v7 W7 C. U% A5 b. z
1205900 ALLEGRO_EDITOR INTERACTIV       additional object polygon-rectangle for "snap to pick"
8 m4 h4 r) ?. a! L( J4 d 1327533 SIP_LAYOUT     REPORTS          Metal Usage Report fails3 o/ Q1 K$ L+ o6 D) S
1341177 ALLEGRO_EDITOR PLACEMENT        "Place Replicate Unmatched Component Interface" window size should be increased to show "Matched Component". j! R- w4 |6 w$ z/ V' N
1360269 SIP_LAYOUT     REPORTS          Getting incorrect results in the Metal Usage report of SiP Layout when the variable METAL_USAGE_REPORT_NOARCS is set' A$ T( U2 Q3 j
1361281 ALLEGRO_EDITOR INTERACTIV       Moving stacked vs non-stacked via's should be the same.6 R  Z  ]1 s1 q( t- H: m
1366525 ALLEGRO_EDITOR INTERACTIV       Add replace via with via structure command to Allegro PCB
% a% L9 m& j* Y2 i 1368091 ALLEGRO_EDITOR INTERACTIV       Snap pick to fuction should see fiiled rectangle as a shape
: M' d# V- U8 b$ t2 L7 n4 q" H6 R 1371510 APD           DATABASE         How to show DRC when tack point of wirebond out of finger boundary
, `; {. U/ A2 ?1 R; e 1373564 ASI_PI         GUI              Impedance results are incorrect in PFE
* T/ R/ [$ I# e1 `' M7 Y. V& T 1374703 ALLEGRO_EDITOR SHAPE            Inconsistent behavior on shape voiding5 m9 O3 x/ b( r/ g
1376851 CONSTRAINT_MGR UI_FORMS         CM workbooks change after simulating' A6 c  E3 U4 V  i" I( W1 s, Z+ u
1377555 ALLEGRO_EDITOR DRC_CONSTR       The "Line to SMD Pin Same Net Spacing" DRC toggles everytime we run "Force Update" of Dynamic Shapes.
9 ?$ o/ C- n" ^, p! w2 A3 } 1378032 ALLEGRO_EDITOR REPORTS          Report command and batch mode give different Waived DRC Report results in PCB Editor' `! m* Q$ J& T& _) y' O
1378611 ALLEGRO_EDITOR INTERFACES       Enable STEP export to convert the mixed unit into one single unit1 Z! A9 B5 }! ^# Z- |" Y6 Z( R
1379240 APD            PLACEMENT        Placement gives error regarding the difference in units between the database and symbol, which is not the case
' R5 ^3 E; K' S" z1 F6 ^; w. f 1394908 ALLEGRO_EDITOR DATABASE         Database crashes on doing "Show Element" on selected net& ^8 p. |( W; m  }  q9 G3 L
1395541 ALLEGRO_EDITOR PLOTTING         Export PDF not correct for Phantom lines4 f: k" u. q5 L/ s8 g
1395747 CONSTRAINT_MGR INTERACTIV       Rename refdes causes Allegro to crash. Possibly due to CM being open." B8 w. Z' c1 c& N3 Z+ N; T
1396915 APD            STREAM_IF        The question about MIRROR geometry function from stream out
& ^% d" m/ k2 Z- X1 @ 1398184 ALLEGRO_EDITOR MANUFACT         Mismatch in backdrill data with IPC-2581 export

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2#
发表于 2015-5-7 09:08 | 只看该作者
谢谢楼主分享!

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3#
发表于 2015-5-7 10:18 | 只看该作者
现在补丁小了好多了,试试

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4#
发表于 2015-5-7 13:20 | 只看该作者
是不是和原来16.6的升级方式一样?

点评

是的  详情 回复 发表于 2015-5-8 03:38

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5#
发表于 2015-5-7 13:59 | 只看该作者
打上补丁,在运行下破解就行了

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6#
发表于 2015-5-7 14:41 | 只看该作者
可以转低版本了吗?

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7#
 楼主| 发表于 2015-5-8 03:38 | 只看该作者
zxpchx 发表于 2015-5-7 13:20
- M, H. I/ W- e是不是和原来16.6的升级方式一样?
! _) {+ R( s$ }5 s4 ^
是的$ @% K/ n/ S4 n: l( W
  • TA的每日心情
    开心
    2024-2-21 15:59
  • 签到天数: 313 天

    [LV.8]以坛为家I

    8#
    发表于 2015-5-8 11:30 | 只看该作者
    更新太勤快,希望Cadence能出一个实时联网设计的功能

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    9#
    发表于 2015-5-11 12:54 | 只看该作者
    上次论坛不是发过一个? 不是说不是独立的安装文件?
  • TA的每日心情
    擦汗
    2019-12-12 15:00
  • 签到天数: 13 天

    [LV.3]偶尔看看II

    10#
    发表于 2015-5-11 12:58 | 只看该作者
    暫時還沒用到17.0的,- m' S  D% D% ]8 m4 w
    先下來放著先囉!!, v% V6 U" o5 Y# H& o9 p, h
    感謝大大的分享了..
  • TA的每日心情
    奋斗
    2024-1-17 15:52
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    [LV.7]常住居民III

    11#
    发表于 2015-5-11 17:12 | 只看该作者
    謝謝分享喔

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    13#
    发表于 2015-5-12 20:19 | 只看该作者
    这个很赞呀,可惜了,我用17。0有问题。不知道你们有木有,我觉得破解有点问题

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    14#
    发表于 2015-5-13 14:38 | 只看该作者
    感谢,哪位成功了呀!!!!!!!!
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    开心
    2021-8-27 15:55
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    [LV.1]初来乍到

    15#
    发表于 2015-5-14 16:35 | 只看该作者
    安装补丁后,c:\4.png
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