allegro design entry HDL打开文件报错，求指点

lili0921

allegro design entry HDL打开文件报错，提示如下
csnetlister 16.6-p001 (v16-6-112A) 9/10/2012
) d& c! Z7 E4 {' |5 h* {
Info: Cell 'r' not found in library 'analog'. The cell is being used from library RF_comp_lib.
Error:  Error occured while reading the following pc.db file in design 'sn5'
2 a3 S* e3 B2 } Ensure that the library 'Pspice_elem' contains the cell 'capacitor' in the physical library folder. Also ensure that the logical library name is present in the .cpm and cds.lib files and does not contain any uppercase letters.
8 g! R0 I7 m9 C  f( VInfo: Cell 'c' not found in library 'analog'. The cell is being used from library rf_comp_lib.
Netlist Log File: temp/csnetlister.log
( n# U6 O( I, r0 \- dcsnetlister.exe exited with errors.

求大神指点要怎么办？
5 Y  M2 d$ p/ {& o4 A

霹雳风雷

capacitor，应该是这个CAE symbol有问题，看看analog库中是不是没有包含，或者器件有问题。