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偶也跟一贴！
8 q3 U4 E3 F+ ~2 f9 Z9 E: S) z以下内容来自《high speed digital system design》。- Q, s- P: G' d0 W+ G
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A via is a small hole drilled through a PCB that is used to make connections between various
# T. R2 x2 C. C+ }# zlayers of the PCB or to connect components to traces. It consists of the barrel, the pad, and
* {% C- f& E# h+ @the antipad. The barrel is a conductive material that fills the hole to allow an electrical4 A) q! i2 F9 v; ^7 S0 B5 _
connection between layers, the pad is used to connect the barrel to the component or trace,& N8 w& I4 V* \$ K5 ?, F# D
and the antipad is a clearance hole between the pad and the metal on a layer to which no/ I# R2 _: J2 V
connection is required. The most common type of via is called a through-hole via because it
0 O. V3 d6 } \9 ?- g- ^is made by drilling a hole through the board, filling it with solder, and making connections on
: ~* w9 a7 v6 u! r7 D6 j+ oappropriate layers via the pad. Other, less common types of vias, used primarily in multichip- C. ]/ L7 U; C: O0 t7 r
modules (MCMs) and advanced PCBs, are blind, buried, and micro-vias. Figure 5.1 depicts3 z& L; V' t3 c) G. @
a typical through-hole via and its equivalent circuit. Notice that the pads used to connect the
: C* r" [) Q8 Ptraces on layers 1 and 2 make contact with the barrel and that there is no connection on
4 f8 P0 {$ l t9 Ilayer 3. Blind and buried vias have a slightly different construction. Since through-hole vias
+ ^* P% |' e- T7 M) Yare by far the most common used in industry, they are the focus of this discussion.
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Notice that the via model is simply a pi network. The capacitors represent the via pad# G" }, S0 @: I$ `# S/ e3 f. f, U
capacitance on layers 1 and 2. The series inductance represents the barrel. Since the via
0 o. ^* g/ J6 J; Kstructures are so small, they can be modeled as lumped elements. This assumption, of
( B1 N! I5 F$ Q4 Lcourse, will break down when the delay of the via is larger than one-tenth of the edge rate.
: b; `( q' C5 O9 N; x0 d+ X$ `$ k+ SThe main effect that via capacitance has on a signal is that it will slow down the signal edge+ V% @- M V/ |, o/ o$ T4 O& x
rate, especially after several transitions. The amount that the signal edge rate will be slowed3 G+ z0 M% z: L9 H
can be estimated by examining the degradation of a signal transmitted through a capacitive6 b+ N: ^% Z. O" B, ?
load, as shown later in this chapter in equation (5.21). Furthermore, if several consecutive8 ^# @8 F2 W! c8 e/ w( a
vias are placed in close proximity to one another, it will lower the effective characteristic* Y V. L1 |6 |' A$ V. Y$ P, x
impedance, as explained in Section 5.3.3. The approximate value of the pad capacitance is
( |* C* A: h) S. Q8 q! Z, x[Johnson and Graham, 1993]
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3 Q/ z/ E8 @ G; w8 R[ 本帖最后由 killerljj 于 2007-11-21 20:51 编辑 ] |
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发表于 2007-9-11 14:20
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支持！
反对！
发表于 2008-1-17 21:53
7 M5 W- D/ \" t" I8 d" D3 v/ g
发表于 2007-9-15 15:34
俺也顶一下,因为焊盘描述的太形象啦!